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Silicon Labs /Series1 /EFM32GG11B /EFM32GG11B420F2048GQ100 /QSPI0 /DEVINSTRRDCONFIG

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Interpret as DEVINSTRRDCONFIG

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31282724232019161512118743000000000000000000000000000000000000000000RDOPCODENONXIP0INSTRTYPE0 (DDREN)DDREN0ADDRXFERTYPESTDMODE0DATAXFERTYPEEXTMODE0 (MODEBITENABLE)MODEBITENABLE0DUMMYRDCLKCYCLES

Description

Device Read Instruction Configuration Register

Fields

RDOPCODENONXIP

Read Opcode in Non-XIP Mode
INSTRTYPE

Instruction Type
DDREN

DDR Enable
ADDRXFERTYPESTDMODE

Address Transfer Type for Standard SPI Modes
DATAXFERTYPEEXTMODE

Data Transfer Type for Standard SPI Modes
MODEBITENABLE

Mode Bit Enable
DUMMYRDCLKCYCLES

Dummy Read Clock Cycles

Links

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Register License

  • SPDX-License-Identifier: Zlib
  • The licensor of this software is Silicon Laboratories Inc.
  • This software is provided ‘as-is’, without any express or implied
  • warranty. In no event will the authors be held liable for any damages
  • arising from the use of this software.
  • Permission is granted to anyone to use this software for any purpose,
  • including commercial applications, and to alter it and redistribute it
  • freely, subject to the following restrictions:
    1. The origin of this software must not be misrepresented; you must not
  • claim that you wrote the original software. If you use this software
  • in a product, an acknowledgment in the product documentation would be
  • appreciated but is not required.
    1. Altered source versions must be plainly marked as such, and must not be
  • misrepresented as being the original software.
    1. This notice may not be removed or altered from any source distribution.
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Register Reference

https://github.com/cmsis-svd/cmsis-svd-data